Synopsys Spyglass 2026.09

Description

---

🔎 Synopsys SpyGlass Y-2026.09 (VC SpyGlass) — Full RTL Signoff Suite

✅ Synopsys SpyGlass Y-2026.09 is the September 2026 feature train of VC SpyGlass, the static RTL signoff platform used for lint, clock domain crossing (CDC), reset domain crossing (RDC), power, DFT/testability, and functional-safety guidance.

📌 Catch structural and electrical bugs at RTL — before synthesis, before long simulations, and before a costly silicon respin. Y-2026.09 belongs to Synopsys’ Y Foundation (2026.03 / 2026.06 / 2026.09) under the Synchronized Release Model. Official module names, service packs such as Y-2026.09-SP1, and the complete “What’s New / Fixed Issues” list are published only on SolvNetPlus for licensed customers.

---

🎯 Who this release is for

• 🖥️ ASIC / SoC RTL and integration teams doing block and full-chip signoff
• ⏱️ CDC/RDC owners on multi-clock, multi-reset, UPF low-power designs
• 🔋 Power architects who need clock-gating and RTL power insight early
• 🛡️ Automotive / aero teams mapping ISO 26262 or DO-254 coding and safety checks
• 🧩 FPGA groups that still need production-grade lint + CDC at RTL

---

🧩 What’s in the SpyGlass / VC SpyGlass family

✔️ VC SpyGlass Lint

Coding style, synthesizability, semantic and structural checks, reuse rulesets (STARC, OpenMORE), and company-custom rules. Formal-assisted functional lint finds deeper RTL bugs without a testbench. ML-assisted root-cause grouping helps when violation counts explode on large SoCs.

✔️ VC SpyGlass CDC

Low-noise CDC signoff: missing synchronizers, reconvergence, data-hold / fast-to-slow loss, protocol checks (handshake, FIFO), quasi-static signals, SDC- and UPF-aware instrumentation. Structural + in-built formal functional CDC in one methodology. Hierarchical abstract models for SoC capacity.

✔️ SpyGlass RDC

Asynchronous reset crossings inside the same clock domain — a growing respin cause as multi-phase boot and power sequences add reset domains. Same architecture as CDC: auto extract clocks/resets, low false-fail noise, RDC-centric debug.

✔️ SpyGlass Power

RTL and gate-level power estimate from FSDB / VCD / SAIF, clock-gating ratio (CGR) and efficiency (CGE), exploration of fine/coarse gating and memory access before you freeze the architecture.

✔️ VC SpyGlass Fault Analysis & TestMAX Advisor

Static ISO 26262-oriented metrics (transient/permanent), hotspot registers for SPFM improvement, and RTL testability guidance on the same engine — no production testbench required for the static pass.

---

🚀 Highlights teams :

• 🧠 Shift-left RTL signoff — lint + CDC + RDC + power in one platform tied to the RTL source
• 📉 Low-noise CDC — control/data correlation, widest synchronizer recognition, fewer junk violations
• 🔗 Constraint consistency — SDC/UPF use models aligned with Design Compiler, Fusion Compiler, and PrimeTime
• ⚙️ Simple setup — auto-extract clocks, resets, and domains; or jump-start from existing SDC
• 🐛 Verdi debug — cross-probe violation → RTL → schematic → instrumented power cells
• 📦 SoC scale — hierarchical flows and signoff abstract models for full-chip roll-up
• 📝 Languages — Verilog, VHDL, SystemVerilog, mixed-language IP integration
• 🤖 Modern stack — fits CI check-in gates, waiver discipline, and Synopsys.ai / Cloud assistive workflows where your site enables them

---

💻 System requirements (Y Foundation) :

Platform matrix is from Synopsys’ public compute-platforms roadmap. Always confirm the exact SpyGlass / VC SpyGlass installer for your OS on SolvNetPlus — not every binary ships on every OS.

• 🐧 Linux: RHEL 8.4+ and 9.x · SLES 15-SP3+ · Rocky Linux 8.4+ and 9.x · AlmaLinux 8.4+ and 9.x
• 🪟 Windows (when offered): Windows 11 · Windows Server 2022 · Windows Server 2025
• 🔑 Licensing: Synopsys SCL / FlexNet; separate features for Lint, CDC, RDC, Power, Fault as purchased
• 🧰 Typical companions: Verdi · VCS · Design Compiler or Fusion Compiler · PrimeTime · UPF 2.x/3.x · SDC
• ☁️ Optional: Synopsys Cloud / containerized farm installs per your CAD policy

---

🛠️ New functions, service packs & bug fixes in 2026.09 :

⚠️ Synopsys does not publish a public changelog for VC SpyGlass Y-2026.09. Do not copy unofficial “feature lists” from forums into production pages.

After you receive the bits, use these official sources only:

• 📥 SolvNetPlus Download Center → VC SpyGlass / SpyGlass → Release Notes / What’s New
• 📚 Installed documentation: user guide + Fixed Issues for Y-2026.09 and any SP
• 🩹 Service packs on this train look like Y-2026.09-SP1, Y-2026.09-SP2 — install the SP your CAD team qualifies before signoff

Typical SP content on this product (pattern across prior trains, not a 2026.09 claim): parser/language updates, CDC/RDC noise reduction, UPF instrumentation fixes, Verdi cross-probe repairs, hierarchical model bugs, and license/runtime patches. Paste only bullets you copy from SolvNet.

---

💡 Interesting facts :

• 🏷️ The name SpyGlass predates Synopsys. It was created by Atrenta. Synopsys bought Atrenta in 2015 and kept the brand because “run SpyGlass” already meant RTL lint + CDC worldwide.
• 🔄 The next-gen product was folded into Verification Continuum as VC SpyGlass — same franchise, shared compile/debug with VCS and Verdi, built for full-chip capacity.
• ✈️ Beyond mobile and HPC SoCs, SpyGlass rule packs are used in flows that target DO-254 airborne electronic hardware and ISO 26262 automotive RTL discipline.
• 📅 Letter + date versioning (Y-2026.09) is not a marketing number. Y is the 9-month compute foundation; 2026.09 is the September feature opportunity (second Monday of the month in the SRM calendar).

---

📦 What you should list on the order / delivery note :

• Product: Synopsys SpyGlass / VC SpyGlass
• Train: Y-2026.09 (+ latest qualified SP)
• Modules: Lint · CDC · RDC · Power · Fault / TestMAX Advisor (as licensed)
• Delivery: SolvNetPlus media + license keys (not a consumer download)

---

❓ FAQ :

Is SpyGlass the same as VC SpyGlass?
SpyGlass is the historic product name. VC SpyGlass is the current Verification Continuum generation. Most 2026 sites run VC SpyGlass; docs and licenses may still say SpyGlass.

Can I use Y-2026.09 with an older VCS or Verdi?
Stay on the same foundation when you can (Y with Y). Mixed-foundation stacks work only if SolvNet compatibility notes say so.

Does this page include every 2026.09 bug fix?
No. Only SolvNetPlus release notes are authoritative. This description covers the product scope, Y-foundation platforms, and how to find the official delta.

Synopsys, SpyGlass, VC SpyGlass, Verdi, VCS, Design Compiler, Fusion Compiler, PrimeTime, and Synopsys.ai are trademarks of Synopsys, Inc. Platform requirements summarized from Synopsys compute-platforms documentation. Version strings and features are as delivered on SolvNetPlus for your contract.

---

⭐⭐⭐⭐⭐ SoC RTL signoff workhorse

“We run VC SpyGlass Lint + CDC + RDC as a block check-in gate. Noise is manageable once SDC/UPF is clean, Verdi cross-probe is fast, and we catch metastability and reset issues before synthesis. Y-foundation install on RHEL was uneventful. Not a consumer app — you need a methodology and licenses — but for production RTL handoff it is still the tool customers expect.”
— ASIC verification lead, sample review for product page