Synopsys Spyglass 2023.12 cracked release

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Early Design Analysis Tools Enable Efficient Verification and Optimization of SoC Designs

Using many advanced algorithms and analysis techniques, the SpyGlass platform provides designers with insight about their design, early in the process at RTL. It functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs.

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Description

SpyGlass Lint

Early Design Analysis for Logic Designers

Inefficiencies during RTL design usually surface as critical design bugs during the late stages of design implementation. If detected, these bugs will often lead to iterations, and if left undetected, they will lead to silicon re-spins. The SpyGlass® product family is the industry standard for early design analysis with the most in-depth analysis at the RTL design phase. SpyGlass provides an integrated solution for analysis, debug and fixing with a comprehensive set of capabilities for structural and electrical issues all tied to the RTL description of design.

Introduction

With soaring complexity and size of chips, achieving predictable design closure has become a challenge. A multitude of coding style, structural and electrical design issues can manifest themselves as design bugs and result in design iterations, or worst still—silicon re-spins. Other tools may detect design bugs but often at late stages of design implementation, after a significant investment in time and effort has already been made. As design teams become geographically dispersed, consistency and correctness of design intent becomes a key challenge for chip integration teams. Emphasis on design reuse and IP integration requires that design elements be integrated and meet guidelines for correctness and consistency.

SpyGlass RTL Signoff Chart with SpyGlass Lint at the chart top

Features and Benefits

  • Sophisticated static and dynamic analysis identifies critical design issues at RTL
  • A comprehensive set of electrical rules check to ensure netlist integrity
  • Includes design reuse compliance checks, such as STARC™ and OpenMORE to enforce a consistent style throughout the design
  • Customizable framework to capture and automate company expertise
  • Integrated debug environment enables easy cross-probing among violation reports, schematic and RTL source
  • The most comprehensive knowledge base of design expertise and industry best practices
  • Supports Verilog, VHDL, V2K, SystemVerilog and mixed-language designs
  • Tcl shell for efficient rule execution and design query
  • SoC abstraction flow for faster performance and low noise

SpyGlass CDC

Comprehensive, Low-Noise Clock Domain Crossing Verification

Among the many verification challenges confronting system-on-chip (SoC) designers today, clock domain crossings (CDC) ranks near the top in difficulty. Today’s SoCs have dozens or sometimes even hundreds of asynchronous clock domains, making it very difficult to verify using conventional simulation or static timing analysis (STA). RTL simulation is not designed to verify metastability effects which cause data transfer issues across asynchronous clock boundaries and STA does not address asynchronous clock domains issues.

Introduction

CDC issues have become a leading cause of design errors. Such errors can add significant time and expense to the design-and-debug cycle, and may even find their way into silicon, necessitating costly respins. Besides the traditional CDC issues, Reset Domain Crossing (RDC) issues can also cause metastability in signals. Use of asynchronous resets is becoming more prevalent because of the wider use of multiphase power-up/boot sequences, etc. As a consequence, RDC issues are causing more and more design errors. (Please refer to the SpyGlass RDC Datasheet for more information about these reset domain crossing capabilities.) For both of these types of issues, SpyGlass® provides a high-powered, comprehensive solution.

SpyGlass RTL Signoff Chart with clock domain crossing verification on the chart

Features and Benefits

  • Protocol Independent Analysis, recognition of widest variety of synchronizers and auto detection of quasi-static signals resulting in the lowest number of false violations
  • Architecture for scalable CDC and RDC verification
  • Simple setup by automatically extracting the clock, reset and clock domains information; It can also extract the same information from existing SDC constraints providing a jump start to the users
  • Comprehensive structural and functional analysis using formal based and simulation based solutions to deliver signoff quality
  • Highest performance and CDC/RDC centric debug capabilities
  • Hierarchical SoC flow to support IP based design methodologies to deliver quickest turnaround time for very large size SoCs
  • Integrated with other SpyGlass solutions for RTL signoff for lint, constraints, DFT and power
  • Low learning curve and ease of adoption

SpyGlass RDC

Comprehensive, Low-Noise Reset Analysis

Clock domain crossings (CDCs) are a well-known source of metastability. However, they are not the only source. Asynchronous reset crossings within a same clock domain can also cause metastability. Use of asynchronous resets is becoming more prevalent because of the wider use of multiphase power-up boot sequences. As a consequence, Reset Domain Crossing (RDC) issues are causing more and more design errors. Such errors can add significant time and expense to the design and debug cycles, and may even find their way into the silicon, necessitating costly respins. Like CDC verification, RDC verification is equally important to ensure that the designs work as expected. For both of these, you need a high-powered, comprehensive solution.

Comprehensive RDC Analysis

SpyGlass® RDC provides the comprehensive solution to address reset crossing domain issues early at RTL. This solution avoids costly respins and:

  • Leverages industry standard SpyGlass CDC architecture
  • Offers simple setup to automatically extract the clock, reset and clock domain information
  • Recognizes standard design techniques resulting in the lowest number of false violations
  • Provides high-performance runtime and RDC-centric debug capabilities
  • Offers short learning curve and easy adoption into existing workflows
  • Integrates within the SpyGlass RTL signoff solution which targets other analysis, for lint constraints, DFT and power
SpyGlass RTL Signoff Chart with reset domain crossing verification on the chart

SpyGlass Constraints

Specify Early, Validate Continuously and Automate Handoff

Quality of constraints dictates the quality and speed of implementation. Constraints impact is multidimensional spanning synthesis, timing analysis, and physical design. More than 25 percent of design projects go through more than ten iterations due to constraints issues. The burden of overall constraints effectiveness is on the design engineers across the development process. The SpyGlass® Constraints solution addresses these challenges with a broad-based solution starting early in design process and providing an environment to validate continuously.

Introduction

Creating and ensuring correct and consistent constraints, at all levels of the design hierarchy and throughout the design cycle, is a vital and increasingly challenging task. The difficulties can include: writing new constraints, managing thousands of lines of legacy constraints, managing thousands of timing exceptions, experiencing unwanted iterations due to changing constraints and implementing erroneous constraints resulting in redesigns or even respins.

The SpyGlass Constraints solution provides a productivity boost to IC design efforts by automating the validation of constraints. SpyGlass Constraints verifies that existing constraints are correct and consistent early in the design flow.

The SpyGlass solution can trim weeks or more from design schedules by pinpointing the root cause of constraint problems. By ensuring valid constraints, SpyGlass Constraints can eliminate design flaws and costly respins.

Features and Benefits

• Ensures that constraints are correct and consistent throughout the design flow, early at RTL
• Can save weeks or months of manual creation and verification effort
• Supports full Tcl-based SDC, compliant with Design Compiler® and PrimeTime®
• Flags redundant and over-specified constraints

SpyGlass Power

The Complete Solution for Power Optimization at RTL

Power management techniques, which were once only deployed for wireless applications, have now become ubiquitous. All IC designers now need to configure their RTL for efficient power partitioning along with reduced static and dynamic consumption. This is especially true for more advanced technology nodes. These configurations involve iteratively performing power estimation, profiling and reduction to assess and improve the power efficiency of the design.

Introduction

Every milliwatt of power matters, regardless of the application. Designers can no longer wait for the final netlist to get accurate power numbers, as full visibility is needed as soon as RTL coding starts, when the most rewarding modifications can be made. At smaller technology nodes, dynamic power is becoming increasingly more dominant and the reduction of overall activity has become a necessity. As designs become vastly larger, designers need a tool that pinpoints the major power gluttons while suggesting modifications with the highest ROI.

SpyGlass RTL Signoff Chart with power estimation and exploration on the chart

Features and Benefits

  • Integrated solution covering all aspects of power analysis including early RTL estimation and exploration
  • Input agnostic
    • Works at RTL or gate-level
    • Supports dynamic activity through FSDB, VCD and SAIF
  • Proven accuracy of power estimation through a calibration toolbox and use of existing data from reference design
  • Various actionable profiling metrics such as Clock Gating Ratio (CGR) and Clock Gating Efficiency (CGE)
  • Wide breadth of power exploration techniques including fine and coarse grain clock gating, micro-architectural modifications and memory access optimization
  • Integration with Verdi® HW/SW Debug for multi-scenario Clock Gating Efficiency analysis and improvement
  • Complementary to downstream implementation tools as it prepares RTL for better inferred clock gating during synthesis
  • RTL signoff solution (power budget and CGE efficiency)

SpyGlass for FPGA Designs

Asynchronous Clock Domain Crossing Analysis

Among the many verification challenges confronting FPGA designers, clock domain crossings (CDC) ranks near the top in difficulty. Today’s designs have dozens of asynchronous clock domains, making it difficult to verify using conventional simulation or static timing analysis (STA). The SpyGlass® product family is the industry standard for early design analysis with the most in-depth analysis at the RTL design phase. SpyGlass provides an integrated solution for analysis, debug and fixing with a comprehensive set of capabilities for structural and electrical issues all tied to the RTL description of design.

Introduction

With the growth in complexity of FPGA designs and higher integration of complex IP, it is becoming increasingly more difficult to verify these designs. Current analysis is limited by timing verification, functional simulation and a cumbersome manual review process. Additionally, due to the integration of complex IP (SERDES, PCIe and USB), the number of asynchronous clocks in FPGA designs has also increased significantly.

Clock Domain Crossing issues have become a leading cause of FPGA design errors, which adds significant time and expense to the design-and-debug cycle. These errors are intermittent and very difficult to debug during the development process.

How SpyGlass for FPGA Designs can fix metastability issues due to asynchronous clock domain crossing

Metastability Issues Due to Asynchronous Clock Domain Crossing

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